The IEEE International Symposium on DEFECT and FAULT TOLERANCE in VLSI SYSTEMS Self-Reconfigurable Mesh Array System on FPGA

Massively parallel computers consisting of thousands of processing elements are expected to be high-performance computers in the next decade. One of the major issues in designing massively parallel computers is the reconfiguration strategy in order to provide an efficient fault tolerance mechanism to avoid defective processors in such large scale systems. This paper develops a self-reconfigurable mechanism of mesh array for easy hardware implementation using local defect information. Compared to those of previous reconfigurable architecture, the proposed selfreconfigurable mechanism achieves almost the same system yields using only local defect information. A prototype of this self-reconfigurable array is implemented on FPGA and the hardware complexities are also discussed. Stacked-silicon-planes is one of the attractive technology to implement massively parallel computers with the recent progress of VLSI technology. The development of such large scale systems will make numerous applications such as multi-media, computer vision, and modeling physical phenomena possible. However, one of the major issues in designing large scale systems is a reconfiguration strategy to provide an efficient fault tolerance mechanism to avoid defects on silicon planes. To achieve the reconfiguration of massively parallel computers many previous studies have been proposed for mesh array. Kung [1] proposed a track switch model which has a row and a column of spare processing elements (PE) around an !#"$! mesh array and switching circuits and tracks placed between PEs. Defective PEs can be removed from the array by changing each switch function. In this model, an !%"$! array is realized by assigning each faulty PE to a compensation path with a spare PE using the graph theory. Since this model has low hardware overhead involved when changing each inter-connection of adjacent PEs, many studies have focused on this model [2], [3]. However, these reconfigurable strategies require a host computer to calculate the combination of the compensation paths using the global information of faulty PEs. For massively parallel computers, an effective self-reconfiguring mechanism using local defect information is very attractive. Numata and Horiguchi [4] proposed a Bypass and Shift (BS) method using only local defect information. The BS method, however, does not guarantee a fast reconfiguration since it uses recursive signals to avoid deadlocks. Takanami & ' ( [6] proposed a neural algorithm using a Hopfield-type neural network. Although many reconfiguration methods have been proposed, these methods are not hardware oriented because they require complex algorithms or procedures to change all the switch functions. )) This work has been supported in part by #1155802 Grant-in-Aid for scientific research. 240 0-7695-0719-0/00 $10.00 c * 2000 IEEE